1. Field of the Invention
The invention relates to direct memory access (DMA), and more particularly to the DMA engines and the DMA channels.
2. Description of the Related Art
Direct memory access (DMA) is a method for facilitating high speed data transfer between a device and memory without CPU intervention. DMA allows hardware subsystems within a computer to access system memory for reading and/or writing independent of the CPU. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, and sound cards.
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load in which the CPU must copy each piece of data from the source a register, and write it back to the new location, rendering the CPU unavailable for other tasks.
A DMA transfer essentially copies a block of memory from one device to another. While the CPU initiates the transfer, the transfer itself is performed by the DMA engine. In a typical example, a block of memory is moved from external memory to faster, internal (on-chip) memory. Such an operation does not stall the processor, which as a result can be scheduled to perform other tasks. DMA transfers are essential to high performance embedded algorithms and networks.
FIG. 1 shows a block diagram of a computer system 100 executing DMA operations. The computer system 100 includes a microprocessor 102, a system memory 104, and peripheral devices 106 and 108. The peripheral devices 106 and 108 may be disk drive controllers, graphics cards, network cards, sound cards, or any chips requiring mass data transfer such as a network switch chip. The microprocessor 102 includes a CPU 110, a system memory controller 114 controlling the data transfer of the system memory 104, a internal bus controller 112 controlling the internal bus of the microprocessor 102, and DMA engines 0 to N respectively controlling the signaling of DMA operation through DMA channels 0 to N. DMA channels are system pathways used by DMA engines to directly transfer data between system memory 104 and peripheral devices.
Each DMA engine has a dedicated DMA channel. For example, DMA engine 0 can only use DMA channel 0, DMA engine 1 can only use DMA engine 1, and DMA engine N can only use DMA engine N. Each DMA channel is connected between DMA engines of opposite sides for negotiating data transfer. For example, DMA channel 0 is connected between the DMA engine 0 of microprocessor 102 and the DMA engine 130 of peripheral device 106, and DMA channel N is connected between the DMA engine N of microprocessor 102 and the DMA engine 134 of peripheral device 108. Each device may have multiple DMA engines, such as microprocessor 102 and peripheral device 106. Two kinds of signal, a DMA request (DREQ) signal and a DMA acknowledge (DACK) signal, are transmitted on a single DMA channel for directing data transfer.
FIG. 2 shows a flowchart of a method 200 for executing a DMA operation with a DMA engine. The device driver first selects a DMA engine for data transfer among the multiple DMA engines of the device in step 202. Because each DMA engine has multiple configuration registers associated with it, the DMA engine's configuration registers have to be set up in step 204 before initiating the data transfer. Typical configuration registers are address registers storing starting address of source and target data, count registers storing transfer byte count, and transfer mode registers indicating single or demand mode. The direction of the data transfer, read or write, is determined in step 206. The DMA engine then transmits the DREQ signal and receives the DACK signal through the DMA channel to direct data transfer in step 208. When the transfer is complete, the device interrupts the CPU in step 210, and the CPU checks whether the DMA operation is successful or has failed.
However, because each DMA engine has dedicated DMA channel, there is no sharing of DMA channels. If two DMA engines try to use the same DMA channel at the same time, the signal transmitted on the DMA channel will be mixed and errors induced. Since DMA channels are limited system resources, if multiple devices with multiple DMA engines in the system, too many DMA channels are occupied and the number of devices using the DMA channels is reduced.